The implementation of continuous phase modulation in a transceiver has traditionally relied on using quadrature modulators. As illustrated in FIG. 1, a digital signal processing unit 101 receives the information to be transmitted by a signal 100 and generates the in-phase and quadrature components of the signal. These components are converted to analog signals using digital/analog converters 102a and 102b, and low pass filters 103a and 103b. The output of each filter modulates using multipliers 104a and 104b, one of two carriers 105a or 105b that are separated by 90.degree. in phase. The outputs of the multipliers are then summed in an adder 106 to form the signal 107 which is to be amplified and transmitted.
Recently, continuous phase modulation based on using a .DELTA..SIGMA. modulator to control the division factor of a fractional-N phase locked loop was proposed by Riley et al. in "A Simplified Continuous Phase Modulation Technique," IEEE Transaction on Circuits and Systems--II: Analog and Digital Signal Processing, Vol. 41, pp. 321-326, May 1994. Phase locked loop frequency synthesis is a well-known technique for generating one of many related signals from a frequency variable voltage controlled oscillator (VCO). In a phase locked loop (PLL), an output signal from the VCO is coupled to a programmable frequency divider which divides the frequency of the PLL output by a selected number (the "division factor") to generate a frequency divided signal that is supplied to one input of a phase detector. The phase detector compares the frequency divided signal to a reference signal supplied by another fixed frequency oscillator, which, often, is selected for stability of frequency over time and environmental changes. Any difference in phase between the frequency divided signal and the reference signal is output from the phase detector, coupled through a loop filter, and applied to the VCO in a manner which causes the output signal from the VCO to change in frequency such that the phase error between the frequency divided signal and the reference signal is minimized. With a constant division factor, the output frequency step size is constrained to be equal to the reference signal frequency. With the phase locked loop, an engineering compromise must be struck between the competing requirements of loop lock time, output frequency step size, noise performance and spurious signal generation.
In order to overcome the limitations of the PLL, programmable frequency dividers capable of effectively dividing by non-integers have been developed. Output frequency step sizes which are fractions of the reference signal frequency are obtained while maintaining a high reference frequency and wide loop bandwidth. The synthesizers are known as fractional-N frequency synthesizers. Furthermore, a .DELTA..SIGMA. modulator can be used to control the frequency divider of the phase locked loop. Characteristics of a .DELTA..SIGMA. modulator are such that the quantization noise at its output tends to be toward the high end of the spectrum. The .DELTA..SIGMA. modulator is a quantizer that uses feedback to reduce the quantization noise in a limited frequency band. For this application, the .DELTA..SIGMA. modulator should preferably have low quantization noise within the bandwidth of the modulation.
As illustrated in FIG. 2, a conventional .DELTA..SIGMA. controlled phase locked loop can be described as consisting of two parts: a .DELTA..SIGMA. modulator 201 and a PLL 202. The output of the .DELTA..SIGMA. modulator 201 is used to control the division factor of a frequency divider in the PLL 202. A more detailed diagram of a conventional .DELTA..SIGMA. controlled phase locked loop modulator is illustrated in FIG. 3. A periodic reference signal 301 of frequency r.sub.ref is fed to a phase detector 302 together with the phase of the output of the frequency divider 306. The output of the phase detector 302 is a pulse that is related to the phase difference between the reference signal and the output of the frequency divider 306. The output of the phase detector 302 is filtered through a loop filter 303 and fed to a voltage controlled oscillator 304. Due to the feedback in the phase locked loop, the frequency of the output 305 of the VCO 304 is driven to equal the reference frequency multiplied by the division factor of the frequency divider 306. Hence, the frequency and the phase of the output of the VCO 304 can be controlled by controlling the division factor. In the .DELTA..SIGMA. controlled phase locked loop modulator, the division factors are generated by using a .DELTA..SIGMA. modulator 310. The division factor of the frequency divider can be changed once every period of the reference frequency. The wave generator 307 generates, based on the information signal 300, the input to the .DELTA..SIGMA. modulator 310. Channel selection can be performed by adding in an adder 308, an offset 309 to the input of the .DELTA..SIGMA. modulator 310. The output of the .DELTA..SIGMA. modulator 310 is then used to control the division factor in the frequency divider 306.
The output of the waveform generator is the instantaneous frequency of the desired modulated signal divided by the reference frequency and sampled at the rate of the reference frequency. The oversampling factor, .eta., of the .DELTA..SIGMA. controlled phase locked loop modulator is EQU .eta.=f.sub.ref /symbol rate.
The input to the .DELTA..SIGMA. modulator is the instantaneous frequency of the desired modulated signal sampled at a rate equal to f.sub.ref. The reference frequency f.sub.ref is chosen high enough and the bandwidth of the PLL wide enough for the modulation to fulfill the spectrum and/or the phase noise requirement on the modulation.
Because the phase locked loop is a low pass filter, with respect to the instantaneous frequency, the phase locked loop can be regarded as a means for reconstruction of the desired modulation signal. By choosing the bandwidth of the phase locked loop sufficiently high for the desired modulation to pass, the output of the VCO consists of a signal corresponding to the desired instantaneous frequency and phase noise corresponding to the quantization noise of the .DELTA..SIGMA. modulator. The phase noise can be reduced by either increasing the oversampling factor or by increasing the roll-off of the filtering performed by the phase locked loop. The latter is difficult without jeopardizing the stability margins of the phase locked loop. As a result, prior systems must rely on the use the high oversampling factors. However, a .DELTA..SIGMA. controlled phase locked loop modulator has many benefits. For example, it enables a cost and space efficient implementation, and guarantees that continuous phase in the modulation as well as channel selection can be controlled in a purely direct and digital manner.
In a mobile station and terminals in cordless cellular and satellite communication systems, or in any other equipment with limited power supply, it is desired to keep the oversampling factor of the PLL as low as possible. With a limited oversampling factor, however, the technique of .DELTA..SIGMA. controlled PLL modulation will fail the spectrum and/or the phase noise requirement on the modulation. This is because the filtering by the PLL will not be able to sufficiently filter the quantization noise without distorting the modulation. Thus, there is a need for a method and apparatus for reducing the amount of quantization noise in the signal applied to the frequency divider from the .DELTA..SIGMA. modulator.